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general description the max5417/max5418/max5419 nonvolatile, linear-taper, digital potentiometers perform the function of a mechanical potentiometer by replacing the mechanics with a simple 2-wire digital interface, allowing communi- cation with multiple devices. each device performs the same function as a discrete potentiometer or variable resistor and has 256 tap points. the devices feature an internal, nonvolatile eeprom used to store the wiper position for initialization during power-up. the fast-mode i 2 c-compatible serial interface allows communication at data rates up to 400kbps, mini-mizing board space and reducing interconnection com- plexity in many applications. each device is available with one of four factory-preset addresses (see the ordering information/selector guide ) and features an address input for a total of eight unique address combinations.the max5417/max5418/max5419 provide three nomi- nal resistance values: 50k ? (max5417), 100k ? (max5418), or 200k ? (max5419). the nominal resistor temperature coefficient is 35ppm/? end-to-end, andonly 5ppm/? ratiometric. this makes the devices ideal for applications requiring a low-temperature-coefficient variable resistor, such as low-drift, programmable gain- amplifier circuit configurations. the max5417/max5418/max5419 are available in a 3mm x 3mm 8-pin tdfn package, and are specified over the extended -40? to +85? temperature range. applications mechanical potentiometer replacementlow-drift programmable-gain amplifiers volume control liquid-crystal display (lcd) contrast control features ? power-on recall of wiper position from nonvolatile memory ? tiny 3mm x 3mm 8-pin tdfn package ? 35ppm/c end-to-end resistance temperature coefficient ? 5ppm/c ratiometric temperature coefficient ? 50k ? /100k ? /200k ? resistor values ? fast i 2 c-compatible serial interface ? 500na (typ) static supply current ? single-supply operation: +2.7v to +5.25v ? 256 tap positions ? 0.5 lsb dnl in voltage-divider mode ? 0.5 lsb inl in voltage-divider mode max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers ___________________________________________________ _____________ maxim integrated products 1 v dd gnd sda scl 8-bit shift register 8-bit latch 8-bit nv memory i 2 c interface a 0 8 8 256 wl 256- position decoder h por max5417max5418 max5419 ordering information/selector guide functional diagram 19-3185; rev 4; 4/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. ** exposed pad. part temp range i 2 c address r (k ) pin-package top mark max5417 leta+ -40? to +85? 010100a 0 50 8 tdfn-ep** aib max5417meta+ -40? to +85? 010101a 0 50 8 tdfn-ep** als MAX5417NETA+ -40? to +85? 010110a 0 50 8 tdfn-ep** alt max5417peta+ -40? to +85? 010111a 0 50 8 tdfn-ep** alu max5418 leta+ -40? to +85? 010100a 0 100 8 tdfn-ep** aic max5418meta+ -40? to +85? 010101a 0 100 8 tdfn-ep** alv max5418neta+ -40? to +85? 010110a 0 100 8 tdfn-ep** alw max5418peta+ -40? to +85? 010111a 0 100 8 tdfn-ep** alx max5419 leta+ -40? to +85? 010100a 0 200 8 tdfn-ep** aid max5419meta+ -40? to +85? 010101a 0 200 8 tdfn-ep** aly max5419neta+ -40? to +85? 010110a 0 200 8 tdfn-ep** alz max5419peta+ -40? to +85? 010111a 0 200 8 tdfn-ep** ama downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers 2 __________________________________________________ _____________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +5.25v, h = v dd , l = gnd, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = +5v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +6.0v all other pins to gnd.................................-0.3v to (v dd + 0.3v) maximum continuous current into h, l, and w max5417...................................................................... 1.3ma max5418...................................................................... 0.6ma max5419...................................................................... 0.3ma continuous power dissipation (t a = +70?) 8-pin tdfn (derate 24.4mw/? above +70?) .........1951mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units dc performance (voltage-divider mode) resolution 256 taps integral nonlinearity inl (note 1) ?.5 lsb differential nonlinearity dnl (note 1) ?.5 lsb end-to-end temperaturecoefficient tc r 35 ppm/? ratiometric temperaturecoefficient 5 ppm/? max5417_, 50 -0.6 max5418_, 100k -0.3 full-scale error max5419_, 200k -0.15 lsb max5417_, 50k 0.6 max5418_, 100k 0.3 zero-scale error max5419_, 200k 0.15 lsb dc performance (variable-resistor mode) v dd = 3v ? integral nonlinearity(note 2) inl v dd = 5v ?.5 lsb v dd = 3v, max5417_, 50k -1 +2 v dd = 3v, max5418_, 100k ? v dd = 3v, max5419_, 200k ? differential nonlinearity(note 2) dnl v dd = 5v ? lsb dc performance (resistor characteristics) wiper resistance r w v dd = 3v to 5.25v (note 3) 325 675 wiper capacitance c w 10 pf max5417_ 37.5 50 62.5 max5418_ 75 100 125 end-to-end resistance r hl max5419_ 150 200 250 k downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers ___________________________________________________ ____________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +5.25v, h = v dd , l = gnd, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = +5v, t a = +25?.) digital inputs v dd = 3.4v to 5.25v 2.4 input high voltage (note 4) v ih v dd < 3.4v 0.7 x v dd v input low voltage v il v dd = 2.7v to 5.25v (note 4) 0.8 v low-level output voltage v ol 3ma sink current 0.4 v input leakage current i leak ? ? input capacitance 5p f dynamic characteristics max5417_ 100 max5418_ 50 wiper -3db bandwidth (note 5) max5419_ 25 khz nonvolatile memory data retention t a = +85? 50 years t a = +25? 200,000 endurance t a = +85? 50,000 stores power supply power-supply voltage v dd 2.70 5.25 v standby current i dd digital inputs = v dd or gnd, t a = +25? 0.5 1 ? programming current during nonvolatile write;digital inputs = v dd or gnd (note 6) 200 400 ? parameter symbol conditions min typ max units analog section max5417_ 500 max5418_ 600 wiper settling time (note 8) t il max5419_ 1000 ns digital section scl clock frequency f scl 400 khz setup time for start condition t su-sta 0.6 ? hold time for start condition t hd-sta 0.6 ? clk high time t high 0.6 ? clk low time t low 1.3 ? timing characteristics (v dd = +2.7v to +5.25v, h = v dd , l = gnd, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = +5v, t a = +25?. see figures 1 and 2.) (note 7) downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers 4 __________________________________________________ _____________________________________ note 1: the dnl and inl are measured with the potentiometer configured as a voltage-divider with h = v dd and l = gnd. the wiper terminal is unloaded and measured with a high-input-impedance voltmeter. note 2: the dnl and inl are measured with the potentiometer configured as a variable resistor. h is unconnected and l = gnd.for the 5v condition, the wiper terminal is driven with a source current of 80? for the 50k ? configuration, 40? for the 100k ? configuration, and 20? for the 200k ? configuration. for the 3v condition, the wiper terminal is driven with a source current of 40? for the 50k ? configuration, 20? for the 100k ? configuration, and 10? for the 200k ? configuration. note 3: the wiper resistance is measured using the source currents given in note 2. for operation to v dd = 2.7v, see wiper resistance vs. temperature in the typical operating characteristics. note 4: the device draws higher supply current when the digital inputs are driven with voltages between (v dd - 0.5v) and (gnd + 0.5v). see supply current vs. digital input voltage in the typical operating characteristics. note 5: wiper at midscale with a 10pf load (dc measurement). l = gnd; an ac source is applied to h; and the w output is mea-sured. a 3db bandwidth occurs when the ac w/h value is 3db lower than the dc w/h value. note 6: the programming current operates only during power-up and nv writes. note 7: scl clock period includes rise and fall times t r and t f . all digital input signals are specified with t r = t f = 2ns and timed from a voltage level of (v il + v ih ) / 2. note 8: wiper settling time is the worst-case 0% to 50% rise time measured between consecutive wiper positions. h = v dd , l = gnd, and the wiper terminal is unloaded and measured with a 10pf oscilloscope probe (see the typical operating characteristics for the tap-to-tap switching transient). note 9: an appropriate bus pullup resistance must be selected depending on board capacitance. refer to the document linked tothis web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf. note 10: the idle time begins from the initiation of the stop pulse. parameter symbol conditions min typ max units data setup time t su-dat 100 ns data hold time t hd-dat 0 0.9 ? sda, scl rise time t r 300 ns sda, scl fall time t f 300 ns setup time for stop condition t su-sto 0.6 ? bus free time between stopand start condition t buf minimum power-up rate = 0.2v/ms 1.3 ? pulse width of spike suppressed t sp 50 ns maximum capacitive load for each bus line c b (note 9) 400 pf write nv register busy time t busy (note 10) 12 ms timing characteristics (continued) (v dd = +2.7v to +5.25v, h = v dd , l = gnd, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = +5v, t a = +25?. see figures 1 and 2.) (note 7) downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers _______________________________________________________________________________________ 5 wiper transient at power-on max5417 toc04 w1v/div v dd 2v/div 4 s/div c l = 10pf tap = 128h = v dd end-to-end resistance % change vs. temperature max5417 toc05 temperature ( c) end-to-end resistance % change 60 35 10 -15 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 85 dnl vs. tap position max5417 toc01 tap position dnl (lsb) 224 192 160 128 96 64 32 -0.20 -0.15 -0.10 -0.05 0 0.10 0.200.05 0.15 0.25 -0.25 0 256 voltage-divider mode tap position inl (lsb) 224 192 160 128 96 64 32 -0.20 -0.15 -0.10 -0.05 0 0.10 0.200.05 0.15 0.25 -0.25 02 5 6 inl vs. tap position max5417 toc02 voltage-divider mode wiper resistance vs. tap position max5417 toc03 tap position resistance ( ? ) 224 192 160 128 96 64 32 100 200 300 400 500 600 700 0 0 256 v dd = 2.7v i src = 50 a typical operating characteristics (v dd = +5v, t a = +25?, unless otherwise noted.) standby supply current vs. temperature max5417 toc06 temperature ( c) standby supply current ( a) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 0 -40 85 wiper resistance vs. temperature max5417 toc07 temperature ( c) resistance ( ? ) 60 35 10 -15 100 200 300 400 500 600 700 0 -40 85 v dd = 2.7v v dd = 3.0v v dd = 4.5v v dd = 5.25v downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers 6 __________________________________________________ _____________________________________ supply current vs. digital input voltage max5417 toc08 digital input voltage (v) supply current ( a) 4 3 2 1 100 200 300 400 500 600 0 05 10k 1k 100 0.001 0.01 0.1 1 10 100 0.0001 10 100k thd+n response max5417 toc09 frequency (hz) thd+n (%) 1:1 ratio20hz to 20khz bandpass inl vs. tap position (max5417) max5417 toc10 tap position inl (lsb) 224 192 160 128 96 64 32 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 -1.0 02 5 6 variable-resistor modev dd = 2.7v i src = 50 a typical operating characteristics (continued) (v dd = +5v, t a = +25?, unless otherwise noted.) inl vs. tap position (max5418) max5417 toc11 tap position inl (lsb) 224 192 160 128 96 64 32 -0.5 0 0.5 1.0 1.5 2.0 -1.0 02 5 6 variable-resistor modev dd = 2.7v i src = 20 a inl vs. tap position (max5419) max5417 toc12 tap position inl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 02 5 6 variable-resistor modev dd = 2.7v i src = 10 a dnl vs. tap position (max5417) max5417 toc13 tap position dnl (lsb) 224 192 160 128 96 64 32 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.3 02 5 6 variable-resistor mode dnl vs. tap position (max5418) max5417 toc14 tap position dnl (lsb) 224 192 160 128 96 64 32 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 02 5 6 variable-resistor modev dd = 2.7v i src = 20 a downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers _______________________________________________________________________________________ 7 -0.2 -0.1 0 0.1 0.2 0.3 -0.3 dnl vs. tap position (max5419) max5417 toc15 tap position dnl (lsb) 224 192 32 64 96 128 160 0 256 variable-resistor modev dd = 2.7v i src = 10 a midscale wiper response vs. frequency (max5417) max5417 toc16 frequency (khz) wiper response (db) 100 10 -25 -20 -10-15 -5 max5417tap = 128 c l = 50pf c l = 10pf 0 -30 1 1000 midscale wiper response vs. frequency (max5418) max5417 toc17 frequency (khz) wiper response (db) 100 10 -25 -20 -10-15 -5 max5418tap = 128 c l = 50pf c l = 10pf 0 -30 11 0 0 0 midscale wiper response vs. frequency (max5419) max5417 toc18 frequency (khz) wiper response (db) 100 10 -40 -35 -30 -25 -20 -15 -10 -5 0 -45 1 1000 max5419tap = 128 c l = 10pf c l = 50pf tap-to-tap switching transient (max5417) max5417 toc19 w10mv/div sda2v/div 1 s/div max5417c l = 10pf from tap 127to tap 128 h = v dd tap-to-tap switching transient (max5418) max5417 toc20 w10mv/div sda2v/div 1 s/div max5418c l = 10pf from tap 127to tap 128 h = v dd tap-to-tap switching transient (max5419) max5417 toc21 w10mv/div sda2v/div 1 s/div max5419c l = 10pf from tap 127to tap 128 h = v dd typical operating characteristics (continued) (v dd = +5v, t a = +25?, unless otherwise noted.) downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers 8 __________________________________________________ _____________________________________ pin description pin name function 1v dd power-supply input. 2.7v to 5.25v voltage range. bypass with a 0.1? capacitor from v dd to gnd. 2 scl i 2 c-interface clock input 3 sda i 2 c-interface data input 4a 0 address input. sets the a0 bit in the device id address. 5 gnd ground 6 l low terminal 7 w wiper terminal 8 h high terminal ? p exposed pad. internally connected to gnd. connect to a large ground plane to maximize thermalperformance. not intended as an electrical point. t hd-sta t su-dat t high t r t f t hd-dat t hd-sta s sr a t su-sta t low t buf t su-sto ps t r t f scl sda parameters are measured from 30% to 70%. detailed description the max5417/max5418/max5419 contain a resistorarray with 255 resistive elements. the max5417 has a total end-to-end resistance of 50k ? , the max5418 has an end-to-end resistance of 100k ? , and the max5419 has an end-to-end resistance of 200k ? . the max5417/max5418/max5419 allow access to the high,low, and wiper terminals for a standard voltage-divider configuration. h, l, and w can be connected in any desired configuration as long as their voltages fall between gnd and v dd . a simple 2-wire i 2 c-compatible serial interface moves the wiper among the 256 tap points. a nonvolatile mem-ory stores the wiper position and recalls the stored wiper position in the nonvolatile memory upon power-up. the nonvolatile memory is guaranteed for 50 years for wiper data retention and up to 200,000 wiper store cycles. figure 1. i 2 c serial-interface timing diagram v dd i ol = 3ma i oh = 0ma v out 400pf sda figure 2. load circuit downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers ___________________________________________________ ____________________________________ 9 analog circuitry the max5417/max5418/max5419 consist of a resistorarray with 255 resistive elements; 256 tap points are accessible to the wiper, w, along the resistor string between h and l. the wiper tap point is selected by programming the potentiometer through the 2-wire (i 2 c) interface. eight data bits, an address byte, and a con-trol byte program the wiper position. the h and l termi- nals of the max5417/max5418/max5419 are similar to the two end terminals of a mechanical potentiometer. the max5417/max5418/max5419 feature power-on reset circuitry that loads the wiper position from non- volatile memory at power-up. digital interface the max5417/max5418/max5419 feature an internal,nonvolatile eeprom that stores the wiper state for ini- tialization during power-up. the shift register decodes the control and address bits, routing the data to the proper memory registers. data can be written to a volatile memory register, immediately updating the wiper position, or data can be written to a nonvolatile register for storage. the volatile register retains data as long as the device is powered. once power is removed, the volatile regis- ter is cleared. the nonvolatile register retains data even after power is removed. upon power-up, the power-on reset circuitry controls the transfer of data from the non- volatile register to the volatile register. serial addressing the max5417/max5418/max5419 operate as a slavethat receives data through an i 2 c- and smbus-com- patible 2-wire interface. the interface uses a serial dataaccess (sda) line and a serial clock line (scl) to achieve communication between master(s) and slave(s). a master, typically a microcontroller, initiates all data transfers to the max5417/max5418/max5419, and generates the scl clock that synchronizes the data transfer (figure 1). the max5417/max5418/max5419 sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on the sda bus. the max5417/max5418/max5419 scl operates onlyas an input. a pullup resistor, typically 4.7k ? , is required on the scl bus if there are multiple masterson the 2-wire interface, or if the master in a single-mas- ter system has an open-drain scl output. each transmission consists of a start (s) condition (figure 3) sent by a master, followed by the max5417/max5418/max5419 7-bit slave address plus the 8th bit (figure 4), 1 command byte (figure 7) and 1 data byte, and finally a stop (p) condition (figure 3). start and stop conditions both scl and sda remain high when the interface isnot busy. a master signals the beginning of a transmis- sion with a start condition by transitioning sda from high to low while scl is high. when the master has fin- ished communicating with the slave, it issues a stop condition by transitioning the sda from low to high while scl is high. the bus is then free for another transmission (figure 3). bit transfer one data bit is transferred during each clock pulse.the data on the sda line must remain stable while scl is high (figure 5). sda start condition scl s stop condition p figure 3. start and stop conditions sda scl *see the ordering information/selector guide section for other address options. 01 a0 msb lsb nop/w ack 0 1 0* 0* figure 4. slave address smbus is a trademark of intel corporation. downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers 10 _________________________________________________ _____________________________________ acknowledge the acknowledge bit is a clocked 9th bit that the recipientuses to handshake receipt of each byte of data (figure 6). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipi- ent pulls down sda during the acknowledge clock pulse, so the sda line is stable low during the high period of the clock pulse. when the master transmits to the max5417/max5418/max5419, the devices generate the acknowledge bit because the max5417/max5418/ max5419 are the recipients. slave address the max5417/max5418/max5419 have a 7-bit-longslave address (figure 4). the 8th bit following the 7-bit slave address is the nop/ w bit. set the nop/ w bit low for a write command and high for a no-operation command.the max5417/max5418/max5419 are available in one of four possible slave addresses (table 1). the first 4 bits (msbs) of the max5417/max5418/max5419 slave addresses are always 0101. the next 2 bits are factory programmed (see table 1). connect the a 0 input to either gnd or v dd to toggle between two unique device addresses for a part. each device must have aunique address to share the bus. therefore, a maxi- mum of eight max5417/max5418/max5419 devices can share the same bus. table 1. max5417/max5418/max5419 address codes address byte part suffix a6 a5 a4 a3 a2 a1 a0 nop/ w l 0 1 0 1 0 0 0 nop/ w l 0 1 0 1 0 0 1 nop/ w m 0 1 0 1 0 1 0 nop/ w m 0 1 0 1 0 1 1 nop/ w n 0 1 0 1 1 0 0 nop/ w n 0 1 0 1 1 0 1 nop/ w p 0 1 0 1 1 1 0 nop/ w p 0 1 0 1 1 1 1 nop/ w sda data stable, data valid change of data allowed scl figure 5. bit transfer 1 scl start condition sda 28 9 clock pulse for acknowledgment acknowledge not acknowledge figure 6. acknowledge downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers ___________________________________________________ ___________________________________ 11 message format for writing a write to the max5417/max5418/max5419 consists ofthe transmission of the device? slave address with the 8th bit set to zero, followed by at least 1 byte of infor- mation (figure 7). the 1st byte of information is the command byte. the bytes received after the command byte are the data bytes. the 1st data byte goes into the internal register of the max5417/max5418/max5419 as selected by the command byte (figure 8). command byte use the command byte to select the source and desti-nation of the wiper data (nonvolatile or volatile memory registers) and swap data between nonvolatile and volatile memory registers (see table 2). command descriptions vreg: the data byte writes to the volatile memory reg- ister and the wiper position updates with the data in thevolatile memory register. nvreg: the data byte writes to the nonvolatile memo- ry register. the wiper position is unchanged. nvregxvreg: data transfers from the nonvolatile memory register to the volatile memory register (wiperposition updates). vregxnvreg: data transfers from the volatile memo- ry register into the nonvolatile memory register. a 0 slave address control byte data byte acknowledge from max5417/max5418/max5419 nop/w 1 byte acknowledge from max5417/max5418/max5419 acknowledge from max5417/max5418/max5419 d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how control byte and data byte map into max5417/max5418/max5419 registers s a a p s a 0 slave address control byte acknowledge from max5417/max5418/max5419 nop/w acknowledge from max5417/max5418/max5419 d15 d14 d13 d12 d11 d10 d9 d8 control byte is stored on receipt of stop condition ap figure 7. command byte received figure 8. command and single data byte received downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers 12 _________________________________________________ _____________________________________ address byte control byte data byte 12345678 9 1011121314151617 18 19 20 21 22 23 2425 26 27 p scl cycle number s a6 a5 a4 a3 a2 a1 a0 ack tx nv v r3 r2 r1 r0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack vreg 0 1 0 1 a2 a1 a0 0 0 0 0 1 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 nvreg 0 1 0 1 a2 a1 a0 0 0 0 1 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 nvregxvreg 0101a2a1a00 01100001 xxxxxxxx vregxnvreg 0101a2a1a00 01010001 xxxxxxxx table 2. command byte summary nonvolatile memory the internal eeprom consists of an 8-bit nonvolatileregister that retains the value written to it before the device is powered down. the nonvolatile register is programmed with the midscale value at the factory. power-up upon power-up, the max5417/max5418/max5419load the data stored in the nonvolatile memory register into the volatile memory register, updating the wiper position with the data stored in the nonvolatile memory register. this initialization period takes 10?. standby the max5417/max5418/max5419 feature a low-powerstandby. when the device is not being programmed, it goes into standby mode and power consumption is typically 500na. applications information the max5417/max5418/max5419 are intended for cir-cuits requiring digitally controlled adjustable resis- tance, such as lcd contrast control (where voltage biasing adjusts the display contrast), or for programma- ble filters with adjustable gain and/or cutoff frequency. positive lcd bias control figures 9 and 10 show an application where the volt-age-divider or variable resistor is used to make an adjustable, positive lcd bias voltage. the op amp pro- vides buffering and gain to the resistor-divider network made by the potentiometer (figure 9) or to a fixed resistor and a variable resistor (see figure 10). programmable filter figure 11 shows the configuration for a 1st-order pro-grammable filter. the gain of the filter is adjusted by r2, and the cutoff frequency is adjusted by r3. use the following equations to calculate the gain (g) and the 3db cutoff frequency (f c ): g r r f rc c =+ = 1 1 2 1 23 v out 30v 5v w h l max5417max5418 max5419 v out 30v 5v w h l max5417max5418 max5419 figure 9. positive lcd bias control using a voltage-divider figure 10. positive lcd bias control using a variable resistor x = don? care. downloaded from: http:///
adjustable voltage reference figure 12 shows the max5417/max5418/max5419 usedas the feedback resistors in multiple adjustable voltage- reference applications. independently adjust the output voltage of the max6160 from 1.23v to v in - 0.2v by changing the wiper positions of the max5417/max5418/max5419. offset voltage and gain adjustment connect the high and low terminals of one potentiometerof a max5417 between the null inputs of a max410 and the wiper to the op amp? positive supply to nullify the offset voltage over the operating temperature range. install the other potentiometer in the feedback path to adjust the gain of the max410 (see figure 13). max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers ___________________________________________________ ___________________________________ 13 w h l max6160 max5417max5418 max5419 +5v gnd v in out adj v 0 ref figure 12. adjustable voltage reference 6 8 1 7 32 w h l r1 5v -5v max410 4 max5417max5418 max5419 figure 13. offset voltage and gain adjustment circuit v out r1 w h l max5417max5418 max5419 r2 v in r3 h w l c figure 11. programmable filter lgnd a0 1 + 2 8 7 hw scl sda v dd tdfn top view 3 4 6 5 max5417max5418 max5419 pin configuration chip information process: bicmos package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw-ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code document no. 8 tdfn-ep t833-1 21-0137 downloaded from: http:///
max5417/max5418/max5419 256-tap, nonvolatile, i 2 c-interface, digital potentiometers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/04 initial release 1 4/04 adding future product 2 8/04 adding new part 3 3/09 changes to add details about exposed pad, corrections to table 2, style edits 1, 8, 12?5 4 4/10 ad d ed l ead - fr ee p ackag es to o r d er i ng infor m ati on , ad d ed s ol d er i ng tem p er atur e to ab sol ute m axi m um rati ng s , cor r ected c ond i ti ons for d i ffer enti al n onl i near i ty i n e l ectr i cal c har acter i sti cs , cor r ected a 0 i n p i n d escr i p ti on , cor r ected fi g ur es 12 and 13 1, 2, 8, 13 downloaded from: http:///

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